Functional safety analysis for chip and IP design, in one traceable model.
FusaChip is an AI-assisted platform that helps semiconductor teams build their safety architecture and run DFA, FMEA, FTA and FMEDA from a single shared model, so analyses stay consistent when the design changes.
Talk to usThe problem
Chip safety work is usually spread across diagrams, spreadsheets, requirements tools and fault-simulation tools. That creates the same issues on almost every project.
Re-entry
The same blocks, failure modes and safety mechanisms are maintained in several places by hand.
Drift
When the architecture changes, FMEA, FMEDA, FTA and dependency analysis fall out of step with each other.
Late findings
Risks from shared power, clock and reset resources often surface late in review or after RTL.
Weak evidence
Diagnostic coverage figures are hard to justify, and fault-injection results rarely flow back into the architecture-level analysis.
The platform
One architecture model with safety semantics: blocks, ports, functional and diagnostic paths, and shared power, clock and reset dependencies. Every analysis reads from that model and keeps its own assumptions and review status.
Dependent-failure analysis
Rule-based checks for shared resources and independence, driven directly by the architecture.
FMEA
Generated from the same failure-mode library, with export for review.
Fault tree analysis
Static fault trees built from the architecture, with simple quantification.
FMEDA
Hardware metrics with the source of each diagnostic-coverage figure recorded, and import of results from existing fault-simulation tools.
FusaChip works alongside the tools teams already use. It imports and exports Excel and standard report formats rather than replacing EDA or requirements tools.
How we use AI
Safety engineering needs results that can be checked and reproduced. Our design keeps AI and calculation strictly apart.
- AI drafts and explains. It helps engineers draft analyses, explain findings and query project data. Each suggestion shows where it came from.
- Engineers decide. Suggestions go to a review queue. Nothing enters the controlled model until a qualified engineer accepts it.
- Code calculates. Safety metrics, rule checks and exports are computed by deterministic, regression-tested code, never by the AI model.
- Everything is traceable. Results can be traced back to the architecture, rules and data they depend on, which supports the user's own tool-confidence evaluation.
Safety goals, integrity-level allocation, failure-rate and coverage justification, and sign-off always remain the responsibility of the customer's engineers.
Where we are
FusaChip is in development and has a working prototype. We are a small, self-funded team with hands-on functional-safety experience in semiconductors, and we are preparing pilots with early design partners. If your team does chip or IP safety work and would like to see a demonstration, we would like to hear from you.
中文简介
FusaChip 是面向芯片与 IP 公司的 AI 辅助功能安全设计与分析平台，覆盖 ISO 26262 和 IEC 61508。平台以一个带安全语义的统一架构模型为核心，DFA、FMEA、FTA、FMEDA 四类分析共享这一模型，架构变更后各项分析保持一致，结果可追溯。
AI 只负责起草、解释和查询，所有安全指标由确定性代码计算，每条建议都要经工程师确认后才写入受控模型。产品目前处于原型阶段，正在准备与早期设计合作伙伴开展试点。欢迎联系：contact@fusachip.com